Phase change memory structure with multiple resistance states and methods of programming  an sensing same

ABSTRACT

A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.

FIELD OF THE INVENTION

The embodiments of the invention relate generally to the field ofsemiconductor devices and, more particularly, to resistive memorydevices, e.g., phase change memory devices, having multiple levelresistance states.

BACKGROUND OF THE INVENTION

Microprocessor-accessible memory devices have traditionally beenclassified as either non-volatile or volatile memory devices.Non-volatile memory devices are capable of retaining stored informationeven when power to the memory device is turned off. Traditionally,however, non-volatile memory devices occupy a large amount of space andconsume large quantities of power, making these devices unsuitable foruse in portable devices or as substitutes for frequently-accessedvolatile memory devices. On the other hand, volatile memory devices tendto provide greater storage capability and programming options thannon-volatile memory devices. Volatile memory devices also generallyconsume less power than non-volatile devices. However, volatile memorydevices require a continuous power supply in order to retain storedmemory content.

Research and development of commercially viable memory devices that arerandomly accessed, have relatively low power consumption, and arenon-volatile is ongoing. One ongoing area of research is in resistivememory cells where resistance states can be programmably changed. Oneavenue of research relates to devices that store data in memory cells bystructurally or chemically changing a physical property of the memorycells in response to applied programming voltages, which in turn changecell resistance. Examples of variable resistance memory devices beinginvestigated include memories using variable resistance polymers,perovskite, doped amorphous silicon, phase-changing glasses, and dopedchalcogenide glass, among others.

FIG. 1 shows a basic composition of a variable resistance memory cellsuch as a phase change memory cell 1 constructed over a substrate 2,having a variable resistance material 4 formed between a bottomelectrode 3 and a top electrode 5. One type of variable resistancematerial may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn asdisclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type ofvariable resistance material may include perovskite materials such asPr_((1-x))Ca_(x)MnO₃ (PCMO), La_((1-x)Ca_(x)MnO₃ (LCMO), LaSrMnO₃(LSMO), GdBaCo_(x)O_(y) (GBCO) as disclosed in U.S. Pat. No. 6,473,332to Ignatiev et al. Still another type of variable resistance materialmay be a doped chalcogenide glass of the formula A_(x)B_(y), where B isselected from among S, Se and Te and mixtures thereof, and where Aincludes at least one element from Group III-A (B, Al, Ga, In, TI),Group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P, As, Sb, Bi), or GroupVII-A (F, Cl, Br, I, At) of the periodic table, and with the dopantbeing selected from among the noble metals and transition metals,including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed inU.S. Pat. Nos. 6,881,623 and 6,888,155 to Campbell et al. and Campbell,respectively. Yet another type of variable resistance material includesa carbon-polymer film comprising carbon black particulates or graphite,for example, mixed into a plastic polymer, such as that disclosed inU.S. Pat. No. 6,072,716 to Jacobson et al. The material used to form theillustrated electrodes 3, 5 can be selected from a variety of conductivematerials, such as tungsten, nickel, tantalum, titanium, titaniumnitride, aluminum, platinum, or silver, among others.

Much research has focused on memory devices using memory elementscomposed of phase changing chalcogenides as the resistance variablematerial. Chalcogenides are alloys of Group VI elements of the periodictable, such as Te or Se. A specific chalcogenide currently used inrewriteable compact discs (“CD-RW”) is Ge₂Sb₂Te₅. In addition to havingvaluable optical properties that are utilized in CD-RW discs, Ge₂Sb₂Te₅also has desirable physical properties as a variable resistancematerial. Various combinations of Ge, Sb and Te may be used as variableresistance materials and which are herein collectively referred to as“GST” materials. Specifically, GST materials can change structuralphases between an amorphous phase and two crystalline phases. Theresistance of the amorphous phase (“a-GST”) and the resistances of cubicand hexagonal crystalline phases (“c-GST” and “h-GST,” respectively) candiffer significantly. The resistance of amorphous GST is greater thanthe resistances of either cubic GST or hexagonal GST, whose resistancesare similar to each other. Thus, in comparing the resistances of thevarious phases of GST, GST may be considered a two-state material(amorphous GST and crystalline GST), with each state having a differentresistance that can be equated with a corresponding binary state. Avariable resistance material such as GST whose resistance changesaccording to its material phase is referred to as a phase changematerial.

The transition from one GST phase to another occurs in response totemperature changes of the GST material. The temperature changes, i.e.,heating and cooling, can be caused by passing differing strengths ofcurrent through the GST material. The GST material is placed in acrystalline state by passing a crystallizing current through the GSTmaterial, thus warming the GST material to a temperature wherein acrystalline structure may grow. A stronger melting current is used tomelt the GST material for subsequent cooling to an amorphous state. Asthe typical phase change memory cell uses the crystalline state torepresent a binary 1 and the amorphous state to represent a binary 0,the crystallizing current is referred to as a write or set currentI_(SET) and the melting current is referred to as an erase or resetcurrent I_(RST). One skilled in the art will understand, however, thatthe assignment of GST states to binary values may be switched ifdesired.

Phase change memory cells known in the prior art typically have twostable resistance states, corresponding to the binary 0 and 1. Thus, aconventional two-state phase change memory cell can store one bit ofinformation. Phase change memory cells with more than two stableresistance states are desirable because they would allow each cell tostore more than one bit of information, thereby increasing memorystorage capacity without significantly increasing storage device size orpower consumption.

Researchers in China have proposed one such multi-state phase changememory cell using stacked calcogenide films as storage media. See Y.Lai, et al., Stacked chalcogenide layers used as multi-stage storagemedium for phase change memory, Appl. Phys. A 84, 21-25 (2006). As shownin FIG. 2A, the proposed multi-state phase change memory cell 200comprises a bottom electrode 201, a pure GST layer 202, a tungsten layer203, a silicon-doped GST layer 204, and a top electrode 205. Thisproposed phase change memory cell 200 provides three relatively stableresistance states (1), (2), and (3), as illustrated by FIG. 2B.Implementing three-state logic with cell 200 is difficult. There is aneed for a multiple bit phase change memory cell which is easilyimplemented and which provides more than three stable resistance states.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a two-state phase change memory cellin accordance with the prior art.

FIG. 2A is a cross-sectional view of a three-state phase change memorycell in accordance with the prior part.

FIG. 2B is a graph of the total resistance of the phase change memorycell of FIG. 2A in response to differing program voltages.

FIG. 3A is a graph of the resistance of each element of a phase changememory cell constructed in accordance with an embodiment disclosedherein in response to differing program voltages.

FIG. 3B is a graph of four stable resistance states of a phase changememory cell constructed in accordance with an embodiment disclosedherein.

FIG. 4 is a flowchart illustrating a method of programming a phasechange memory cell constructed in accordance with an embodimentdisclosed herein.

FIG. 5A is a cross-sectional view of a phase change memory cell havingtwo elements of different lengths in accordance with an embodimentdisclosed herein.

FIG. 5B is a cross-sectional view of a phase change memory cell havingtwo elements of different cross-sectional areas in accordance with anembodiment disclosed herein.

FIG. 6A is a graph of the resistance of each element of a phase changememory cell constructed in accordance with an embodiment disclosedherein in response to differing program voltages.

FIG. 6B is a graph of six stable resistance states of a phase changememory cell constructed in accordance with an embodiment disclosedherein.

FIG. 6C is a cross-sectional view of a phase change memory cell havingthree elements of different lengths in accordance with an embodimentdisclosed herein.

FIGS. 7A-7C are cross-sectional views of a phase change memory cellconfigured as a stack cell in accordance with an embodiment disclosedherein at three stages of formation.

FIGS. 8A-8D are cross-sectional views of a phase change memory cellconfigured as a vertical cell with elements of different lengths inaccordance with an embodiment disclosed herein at four stages offormation.

FIGS. 9A-9F are cross-sectional views of a phase change memory cellconfigured as a vertical cell with elements of different resistivitiesin accordance with an embodiment disclosed herein at various stages offormation.

FIGS. 10A-10C are top-down views of a phase change memory cellconfigured as a planar cell with elements of different lengths inaccordance with an embodiment disclosed herein at three stages offormation.

FIGS. 11A-11E are top-down views of a phase change memory cellconfigured as a planar cell with elements of different resistivities inaccordance with an embodiment disclosed herein at various stages offormation.

FIG. 12 depicts a four-state, voltage-sensing sense amplifier, whichcould be used in conjunction with the multi-state phase change memorycell embodiments disclosed herein.

FIG. 13 depicts a four-state, current-sensing sense amplifier, whichcould be used in conjunction with the multi-state phase change memorycell embodiments disclosed herein.

FIG. 14 illustrates a processor system that includes a memory deviceaccording to an embodiment disclosed herein.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and show by way ofillustration specific embodiments in which the claimed invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice them, and it is to beunderstood that other embodiments may be utilized. The progression ofprocessing steps described is exemplary of embodiments of the invention.However, the sequence of steps is not limited to that set forth hereinand may be changed as is known in the art, with the exception of stepsnecessarily occurring in a certain order.

In one embodiment, two fully-switched phase change material elements arefabricated sharing the same first and second electrodes. The elementsare designed such that their respective resistance curves as a functionof programming voltage are shifted with respect to each other, as shownin FIG. 3A. The shifted resistance curves can be achieved by fabricatingthe elements with different phase change materials or by adjusting oneor more element properties, such as, for example, length, resistivity,cross-sectional area, crystallization temperature, and melting point, asdescribed in greater detail below.

Still referring to FIG. 3A, the curve labeled R(a) corresponds to one ofthe two phase change elements, while the curve labeled R(b) correspondsto the other of the two phase change elements. The suffix “a” or “c”following R(a) and R(b) indicate whether the respective phase changeelement is in an amorphous or crystalline state. For example, the label“R(a)a” indicates the phase change element R(a) is in an amorphousstate. By applying different programming voltages, four stableresistance states labeled (1), (2), (3), and (4) can be achieved. Instate (1), both elements are in low resistance configurations, R(a)c andR(b)c. In state (2), element R(a) is in a high resistance configuration,R(a)a, while element R(b) is in a low resistance configuration, R(b)c.In state (3), element R(a) is in a low resistance configuration, R(a)c,while element R(b) is in a high resistance configuration, R(b)c. Instate (4), both elements are in high resistance configurations, R(a)aand R(b)a.

FIG. 3B is a graph of the combined resistance of the elements R(a) andR(b) plotted in FIG. 3A, i.e. the total resistance of the phase changememory cell. Because the phase change memory cell achieves four stableresistance states, it is able to store two bits of information, i.e. 2²or four discrete values corresponding to its four stable resistancestates. Total resistance level TR(1) corresponds to state (1). Totalresistance level TR(2) corresponds to state (2), and so on.

FIG. 4 illustrates the steps of a method of programming a multi-statephase change memory cell, such as the four-state cell just described,and the final device states. Programming begins with a RESET pulse 402to return elements R(a) and R(b) to an initial amorphous state, i.e.state (4) in which both elements are in a high resistance configuration.A programming voltage 404 is then applied to program the memory cell toone of the four states (1), (2), (3), and (4). The voltage of theprogramming pulse is a function of the value to be stored in the memorycell, as shown in FIG. 3B.

FIG. 5A depicts a phase change memory cell 500 constructed in accordancewith a disclosed embodiment. The cell 500 comprises a first electrode501, a first phase change element 502, a second phase change element503, and a second electrode 505. The phase change elements 502, 503,comprising any suitable variable resistance material, such as, forexample, Ge₂Sb₂Te₅, are each in contact with both of the electrodes 501,505. To achieve different respective resistances, the phase changeelements 502, 503 are formed with different lengths. The first element502 is depicted as being longer than the second element 503, althoughthe reverse is also possible. An elongated portion 501 a of firstelectrode 501 is used to shorten the distance between the firstelectrode 501 and the second electrode 505 in the portion of the memorycell 500 containing the second phase change element 503, therebypermitting the second phase change element 503 to be shorter than thefirst phase change element 502. Alternatively, the first electrode 501could be substantially planar while the second electrode 505 contains alowered portion to make contact with the shorter phase change element503. A dielectric material 514, such as, for example, SiO₂, surroundsthe phase change elements 502, 503.

FIG. 5B depicts a phase change memory cell 510 constructed in accordancewith another disclosed embodiment. The cell 510 comprises a firstelectrode 511, a first phase change element 512, a second phase changeelement 513, and a second electrode 515. The elements 512, 513 are eachin contact with both electrodes 511, 515. Elements 512, 513 have similarresistivity and height but element 513 has a lower melting point and awider cross-sectional area than element 512. Thus, the programmingvoltage and resistance of element 513 is reduced. Because first phasechange element 512 and second phase change element 513 have asubstantially similar length, the raised portion 501 a of firstelectrode 501 shown in FIG. 5A is not required, thereby simplifyingelectrode formation in this embodiment. In an alternative embodiment,element 513 has the same melting point, cross-sectional area, and heightas element 512 but a lower resistivity, thereby achieving a similarlyshifted programming voltage. In yet another alternative embodiment,element 513 has the same cross-sectional area and height as element 512but a lower resistivity and melting point, thereby achieving a similarlyshifted programming voltage. A dielectric material 514 surrounds thephase change elements 512, 513.

Although FIGS. 5A and 5B depict four-state phase change memory cellsconstructed in accordance with disclosed embodiments, the claimedinvention is not so limited and can be expanded to provide an arbitrarynumber of stable resistance states. FIG. 6A shows the resistance curvesfor three phase change elements in a six-state phase change memory cell,e.g. cell 600 of FIG. 6C, constructed in accordance with a disclosedembodiment. The elements are designed such that their respectiveresistance curves as a function of programming voltage are shifted withrespect to each other. The shifted resistance curves can be achieved byfabricating the elements with different phase change materials or byadjusting one or more element properties, such as, for example, length,resistivity, cross-sectional area, crystallization temperature, andmelting point, as described in greater detail below.

Still referring to FIG. 6A, the curve labeled R(a) corresponds to afirst phase change element, the curve labeled R(b) corresponds to asecond phase change element, and the curve labeled R(c) corresponds to athird phase change element. The suffix “a” or “c” following R(a), R(b),and R(c) indicate whether the respective phase change element is in anamorphous or crystalline state. For example, the label “R(b)c” indicatesthe phase change element R(b) is in an crystalline state. By applyingdifferent programming voltages, six stable resistance states labeled(1), (2), (3), (4), (5), and (6) can be achieved. In state (1), allthree elements are in a low resistance, i.e. crystalline, configuration.In state (2), the first element is in a high resistance configurationwhile the second and third elements are in a low resistanceconfiguration. In state (3), the first and second elements are in a highresistance configuration while the third element is in a low resistanceconfiguration. In state (4), the first and second elements are in a lowresistance configuration while the third element is in a high resistanceconfiguration. In state (5), the first element is in a low resistanceconfiguration while the second and third elements are in a highresistance configuration. In state (6), all three elements are in a highresistance, i.e. amorphous, configuration.

FIG. 6B is a graph of the combined resistance of the elements R(a),R(b), and R(c) plotted in FIG. 6A, i.e. the total resistance of thephase change memory cell. Because the phase change memory cell achievessix stable resistance states, it is able to store six discrete values.Total resistance level TR(1) corresponds to state (1). Total resistancelevel TR(2) corresponds to state (2), and so on.

FIG. 6C shows one possible structure of a six-state phase change memorycell 600. The cell 600 comprises a first electrode 601 with elongatedportions 601 a, 601 b, a first phase change element 602, a second phasechange element 603, a third phase change element 604, and a secondelectrode 605. The structure is similar to that of the four-state phasechange memory cell depicted in FIG. 5A and described above, but adds thethird element 604 and a second elongated portion 601 b of firstelectrode 601. Each of the three phase change elements 602, 603, 604 hasa different respective length, causing each to have a differentresistance. Different resistances can also be achieved through othermeans, such as, for example, varying the cross-sectional area of eachphase change element, as described above with reference to FIG. 5B. Adielectric material 606 surrounds the phase change elements 602, 603,604.

Phase change memory cells in accordance with embodiments disclosedherein can be constructed as stack cells. FIGS. 7A-7C illustrate amethod that can be used to form a four-state phase change memory cell asa stack cell. As shown in FIG. 7A, memory cell stack 700 is formedcomprising a first layer of phase change material 701, for exampleGe₂Sb₂Te₅, a dielectric layer 702, for example SiO₂, and a second layerof phase change material 703. The resistivity of the second phase changematerial 703 is altered by doping 704, for example with an O or Ndopant, as shown in FIG. 7B. Conductive sidewalls 705, 706 serve aselectrodes and are formed on either side of the gate stack 700, as shownin FIG. 7C.

Phase change memory cells in accordance with embodiments disclosedherein can also be constructed as vertical cells. FIGS. 8A-8D illustratea method that can be used to form a four-state phase change memory cellas a vertical cell. As shown in FIG. 8A, a bottom electrode 801 isformed with an elevated portion 801 a, as described above with referenceto FIG. 5A. A layer of phase change material 802 is deposited over thebottom electrode 801, as shown in FIG. 8B. The phase change material 802is etched to form two phase change material elements 803, 804, as shownin FIG. 8C. A dielectric material 806 is formed surrounding the phasechange elements 803, 804. A top electrode 805 is then formed over and incontact with the two phase change elements 803, 804 and the dielectricmaterial 806, as shown in FIG. 8D.

In an another vertical cell embodiment, a phase change memory cellconstructed in accordance herewith comprises phase change elements ofthe same length but different phase change material compositions. FIGS.9A-9F illustrate two alternative methods of forming such a phase changememory cell. As shown in FIG. 9A, a bottom electrode 901 is formed.According to one embodiment, two phase change elements 902, 903 of thesame phase change material are then formed over and in contact with thebottom electrode 901, as shown in FIG. 9B. A dielectric material isformed surrounding the phase change elements 902, 903. Alternatively,the dielectric material could be formed first, then etched to formchannels in which the phase change elements 902, 903 are formed. Toachieve different resistances, one of the elements 903 is subjected todoping 905, for example O or N doping, while the other element 902remains pure, as shown in FIG. 9C.

Referring to FIG. 9D, in an alternative embodiment, one phase changeelement 902 is formed of a first phase change material. A dielectricmaterial 906 is formed around the phase change element 902.Alternatively, the dielectric material could be formed first and etchedto form a channel in which the phase change element 902 is formed. Asecond phase change element 903 of a second phase change material havinga different resistivity than the first phase change material 902 isformed in a channel etched in the dielectric material 906 and over andin contact with the bottom electrode 901, as shown in FIG. 9E. Accordingto either embodiment, a top electrode 904 is formed over and in contactwith the phase change elements 902, 903, as shown in FIG. 9F.

Phase change memory cells in accordance with embodiments disclosedherein can be constructed as planar cells. FIG. 10A-C are top-down viewsillustrating a method of forming a four-state phase change memory cellas a planar cell. As shown in FIG. 10A, first and second electrodes1001, 1002 are formed on a substrate (not shown). The first electrode1001 includes an extended portion 1001 a to accommodate phase changematerial elements of differing length, as described previously. A phasechange material 1003 is deposited over the electrodes, as shown in FIG.10B. The phase change material is then patterned to form two phasechange material elements 1004, 1005, both in contact with the first andsecond electrodes 1001 and 1002, as shown in FIG. 10C. A dielectric (notshown) is formed surrounding the phase change elements 1004, 1005.

In an another planar cell embodiment, a phase change memory cellconstructed in accordance herewith comprises phase change elements ofthe same length but different phase change material compositions. FIGS.11A-E are top-down views illustrating two alternative methods of formingsuch a phase change memory cell. As shown in FIG. 11A, first and secondelectrodes 1101, 1102 are formed. According to one embodiment, a phasechange material is deposited over the electrodes, then patterned to formtwo phase change elements 1103, 1104, as shown in FIG. 11B. To achievedifferent resistances, one of the elements 1104 is subjected to doping1105, for example O or N doping, while the other element 1103 remainspure, as shown in FIG. 11C. In an alternative embodiment, one phasechange element 1103 is formed of a first phase change material, as shownin FIG. 11D. A second phase change element 1104 of a second phase changematerial having a different resistivity than the first phase changematerial is formed between and in contact with electrodes 1101 and 1102,as shown in FIG. 11E. A dielectric (not shown) is formed surroundingphase change elements 1103, 1104.

Memory devices with multi-state phase change memory cells, such as theembodiments disclosed herein, must also comprise multi-state senseamplifiers in their readout circuitry. For example, memory devices withfour-state phase change memory cells, such as those depicted in FIGS. 5Aand 5B, require four-state sense amplifiers. FIGS. 12 and 13 depict twopossible sensing schemes for sensing the resistances of four-state phasechange memory cells. Of course, other embodiments and configurations arepossible, including those capable of determining more than four statesas is known by those skilled in the art.

FIG. 12 depicts a four-state, voltage-sensing scheme for a senseamplifier 1200, which could be used in conjunction with the multi-statephase change memory cell embodiments disclosed herein. The senseamplifier 1200 obtains the first bit of the two-bit result by applying afixed read current and determining whether a readout voltagecorresponding to cell resistance R is greater than ½ of the readoutvoltage corresponding to a reference resistance R₀. If R>½R₀ then thefirst bit is 1. Otherwise, the first bit is 0. If the first bit is 0,the sense amplifier obtains the second bit by determining whether thereadout voltage corresponding to resistance R is greater than ⅙ of thereadout voltage corresponding to the reference resistance R₀. If R>⅙R₀then the second bit is 1. Otherwise, the second bit is 0. If the firstbit is 1, the sense amplifier then obtains the second bit by determiningwhether the readout voltage corresponding to cell resistance R isgreater than ⅚ of the readout voltage corresponding to the referenceresistance R₀. If R>⅚R₀ then the second bit is 1. Otherwise, the secondbit is 0. Thus, according to one embodiment, a readout voltagecorresponding to R=0 yields 00, a readout voltage corresponding to R=⅓R₀ yields 01, a readout voltage corresponding to R=⅔ R₀ yields 10, and areadout voltage corresponding to R=R₀ yields 11.

FIG. 13 depicts a four-state, current-sensing scheme for a senseamplifier 1300, which could be used in conjunction with the multi-statephase change memory cell embodiments disclosed herein. As shown, when afixed read voltage is applied, three current sensing comparators 1301,1302, 1303 compare a readout current corresponding to cell resistance Rto reference currents corresponding to reference resistances ⅙R_(0,)½R₀, and ⅚R₀, respectively. The first bit of the two-bit result is theoutput of current sensing comparator 1302. Thus, if the readout currentcorresponding to cell resistance R is smaller than the readout currentcorresponding to ½R₀, then the first bit is 1. Otherwise, the first bitis 0. The second bit of the two-bit result is obtained by passing theoutput of the three current sensing comparators 1301, 1302, 1303 throughlogic gates 1304, as shown. Thus, according to one embodiment, a readoutcurrent corresponding to R=0 yields 00, a readout current correspondingto R=⅓ R₀ yields 01, a readout current corresponding to R=⅔ R₀ yields10, and a readout current corresponding to R=R₀ yields 11.

Multi-state phase change memory cells, including the disclosedembodiments described herein, may be fabricated as part of a memorydevice integrated circuit having one or more arrays of memory cellsconstructed in accordance with embodiments described herein. Thecorresponding integrated circuits may be utilized in a typical processorsystem. For example, FIG. 14 illustrates a typical processor system 1400that includes a memory device 1403 employing improved phase changememory cells in accordance with the embodiments described herein. Aprocessor system, such as a computer system, generally comprises acentral processing unit (CPU) 1401, such as a microprocessor, a digitalsignal processor, or other programmable digital logic devices, whichcommunicates with one or more input/output (I/O) devices 1404 over a bus1405. The memory device 1403 communicates with the CPU 1401 over bus1405 typically through a memory controller.

In the case of a computer system, the processor system 1400 may includeperipheral devices such as removable media devices 1402 (e.g., CD-ROMdrive or DVD drive) which communicate with CPU 1401 over the bus 1405.Memory device 1403 is preferably constructed as an integrated circuit,which includes one or more arrays of phase change memory devices. Ifdesired, the memory device 1403 may be combined with the processor, forexample CPU 1401, as a single integrated circuit.

The phase change memory cells disclosed herein can be formed usingconventional deposition, implantation, and etching techniques well knownin the art. Additionally, and also as well known in the art, the phasechange elements are typically bordered by dielectric material on thesides not in contact with electrodes. It should also be appreciated thatvarious embodiments have been described as using a phase change materialas an exemplary variable resistance material. Embodiments of theinvention may also be formed with other types of variable resistancematerial.

The above description and drawings should only be consideredillustrative of exemplary embodiments that achieve the features andadvantages described herein. Modification and substitutions to specificprocess conditions and structures can be made. Accordingly, the claimedinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

1. A resistive memory cell, comprising: first and second electrodes; anda plurality of phase change resistance elements provided between saidfirst and second electrodes, each of said resistance elements having arespective resistance curve as a function of programming voltage whichis shifted relative to the resistance curves of others of saidresistance elements.
 2. The resistive memory cell of claim 1, whereinthe plurality of phase change resistance elements comprises two phasechange resistance elements.
 3. The resistive memory cell of claim 2,wherein at a first programming voltage the first and second resistanceelements are in a low resistance state, at a second programming voltagethe first element is in a high resistance state while the second elementis in a low resistance state, at a third programming voltage the firstelement is in a low resistance state while the second element is in ahigh resistance state, and at a forth programming voltage the first andsecond elements are in a high resistance state.
 4. The resistive memorycell of claim 2, wherein the first resistance element has a first lengthand the second resistance element has a second length less than thefirst length.
 5. The resistive memory cell of claim 2, wherein thesecond resistance element is doped such that the second resistanceelement has a resistance different than a resistance of the firstresistance element.
 6. The resistive memory cell of claim 1, wherein theplurality of phase change elements comprises three phase changeelements.
 7. The resistive memory cell of claim 6, wherein at a firstprogramming voltage first, second, and third elements are in a lowresistance state, at a second programming voltage the first element isin a high resistance state while the second and third elements are in alow resistance state, at a third programming voltage the first andsecond elements are in a high resistance state while the third elementis in a low resistance state, at a forth programming voltage the firstand second elements are in a low resistance state while the thirdelement is in a high resistance state, at a fifth programming voltage,the first element is in a low resistance state while the second andthird elements are in a high resistance state, and at a sixthprogramming voltage the first, second, and third elements are in a highresistance state.
 8. The resistive memory cell of claim 1, wherein theplurality of phase change resistance elements comprises four or morephase change resistance elements.
 9. The resistive memory cell of claim1, wherein the memory cell is capable of storing at least two bits. 10.A resistive memory, comprising: first and second electrodes; a firstphase change resistance material provided between and in contact withsaid first and second electrodes, said first phase change materialhaving a first resistance curve as a function of programming voltage;and a second phase change resistance material provided between and incontact with said first and second electrodes, said second phrase changematerial having a second resistance curve as a function of programmingvoltage, which is shifted relative to said first resistance curve. 11.The resistive memory of claim 10, wherein at a first programming voltagethe first and second resistance materials are in a high resistancestate, at a second programming voltage the first and second resistancematerials are in a low resistance state, at a third programming voltagethe first resistance material is in a high resistance state and thesecond resistance material is in a low resistance state, and at a fourthprogramming voltage the first resistance material is in a low resistancestate and the second resistance material is in a high resistance state.12. The resistive memory of claim 10, wherein a cross-sectional area ofthe second resistance material is greater than a cross-sectional area ofthe first resistance material.
 13. The resistive memory of claim 10,wherein a crystallization temperature of the second resistance materialis lower than a crystalization point of the first resistance material.14. The resistive memory of claim 10, wherein a melting point of thesecond resistance material is lower than a melting point of the firstresistance material.
 15. The resistive memory of claim 10, wherein thesecond resistance material has a resistivity lower than a resistivity ofthe first resistance material.
 16. The resistive memory of claim 10,wherein the first and second resistance materials have approximately thesame resistivity and length but the second resistance material has alower crystallization temperature, a lower melting point, and a widercross-sectional area than a crystallization temperature, a meltingpoint, and a cross-sectional area of the first resistance material. 17.The resistive memory of claim 10, wherein the first and secondresistance materials have approximately the same crystallizationtemperature, melting point, cross-sectional area, and length, but thesecond resistance material has a lower resistivity than a resistivity ofthe first resistance material.
 18. The resistive memory of claim 10,wherein the first and second resistance materials have approximately thesame cross-sectional area and length but the second resistance materialhas a lower crystallization temperature, a lower melting point, and alower resistivity than a crystallization temperature, a melting point,and a resistivity of the first resistance material.
 19. The resistivememory of claim 10, wherein the memory is a stack cell.
 20. Theresistive memory of claim 10, wherein the memory is a planar cell. 21.The resistive memory of claim 10, wherein the first and secondresistance materials comprise a combination of Ge, Sb, and Te.
 22. Theresistive memory of claim 21, wherein the first and second resistancematerials comprise Ge₂Sb₂Te₅.
 23. The resistive memory of claim 10,wherein the first and second resistance materials are surrounded by adielectric material except on sides in contact with the first or secondelectrodes.
 24. A memory device, comprising: an array of memory cells,each memory cell comprising: first and second electrodes; and aplurality of phase change resistance elements provided between saidfirst and second electrodes, each of said resistance elements having arespective resistance curve as a function of programming voltage whichis shifted relative to the resistance curves of others of saidresistance elements.
 25. The memory device of claim 24, wherein theplurality of phase change elements comprises two phase change elements.26. The memory device of claim 25, wherein at a first programmingvoltage the first and second phase change elements are in a lowresistance state, at a second programming voltage the first phase changeelement is in a high resistance state while the second phase changeelement is in a low resistance state, at a third programming voltage thefirst phase change element is in a low resistance state while the secondphase change element is in a high resistance state, and at a forthprogramming voltage the first and second phase change elements are in ahigh resistance state.
 27. The memory device of claim 24, wherein theplurality of phase change elements comprises three or more phase changeelements.
 28. The memory device of claim 24, wherein each of the memorycells is a vertical cell.
 29. The memory device of claim 24, whereineach of the memory cells is a planar cell.
 30. The memory device ofclaim 24, wherein each memory cell is capable of storing at least twobits.
 31. A processing system, comprising: a processor; and a resistivememory coupled to the processor, said resistive memory comprising: firstand second electrodes; and a plurality of phase change elements arrangedbetween said first and second electrodes, said phase change elementshaving different programming characteristics such that at a firstprogramming voltage all phase change elements are in a high resistancestate, at a second programming voltage all phase change elements are ina low resistance state, and at other programming voltages some of saidphase change elements are in a high resistance state while others are ina low resistance state.
 32. The processing system of claim 31, whereinthe plurality of phase change elements comprises two phase changeelements.
 33. The processing system of claim 31, wherein the pluralityof phase change elements comprises three or more phase change elements.34. The processing system of claim 31, wherein each of the plurality ofphase change elements has a different length.
 35. The processing systemof claim 31, wherein each of the plurality of phase change elements hasapproximately the same resistivity and length but different respectivecrystallization temperatures, melting points, and cross-sectional areas.36. The processing system of claim 31, wherein each of the plurality ofphase change elements has approximately the same crystallizationtemperature, melting point, cross-sectional area, and length butdifferent respective resistivity.
 37. The processing system of claim 31,wherein each of the plurality of phase change elements has approximatelythe same cross-sectional area and length but different respectivecrystallization temperatures, melting points, and resistivities.
 38. Amethod of fabricating a resistive memory cell, the method comprising:forming a first electrode; forming a plurality of phase changeresistance elements in contact with said first electrode, each of saidresistance elements having a respective resistance curve as a functionof programming voltage which is shifted relative to the resistancecurves of others of said resistance elements; and forming a secondelectrode in contact with the plurality of phase change elements. 39.The method of claim 38, wherein at least one of the plurality of phasechange resistance elements is doped with a dopant.
 40. The method ofclaim 39, wherein the dopant is at least one of O, N, and Si.
 41. Themethod of claim 38, wherein the plurality of resistance elements areformed before the second electrode.
 42. The method of claim 38, whereinforming the plurality of phase change resistance elements comprisesdepositing a layer of phase change material, selectively etching thelayer of phase change material to form the plurality of phase changeresistance elements, and depositing a dielectric between each of saidplurality of phase change resistance elements.
 43. The method of claim42, further comprising doping at least one of the plurality of phasechange elements after the etching step.
 44. The method of claim 38,wherein each of the plurality of phase change elements has a differentlength.
 45. The method of claim 38, wherein the plurality of phasechange elements comprises two elements.
 46. The method of claim 38,wherein the plurality of phase change elements comprises three or moreelements.
 47. A method of programming a resistive memory cell havingmultiple level resistance states, the method comprising: applying areset pulse; and applying a programming voltage corresponding to one ofthe multiple level resistance states.
 48. The method of claim 47,wherein the reset pulse returns all resistive elements of the resistivememory cell to an amorphous state.
 49. The method of claim 47, whereinthe multiple level resistance states comprise four resistance states.50. A method of sensing a multi-bit value stored in a resistive memorycell having multiple level resistance states, the method comprising:applying a read current to the memory cell; comparing a readout voltagecorresponding to a resistance of the memory cell to a plurality ofreference voltages; determining the multi-bit value stored in theresistive memory cell based on results of the comparisons.
 51. Themethod of claim 50, wherein the plurality of reference voltagescomprises a first reference voltage approximately equal to ½ of areadout voltage corresponding to a reference resistance, a secondreference voltage approximately equal to ⅙ of a readout voltagecorresponding to the reference resistance, and a third reference voltageapproximately equal to ⅚ of a readout voltage corresponding to thereference resistance.
 52. The method of claim 51, wherein a first bit ofthe multi-bit value is determined by comparing the readout voltagecorresponding to a resistance of the memory cell to the first referencevoltage and a second bit of the multi-bit value is determined bycomparing the readout voltage corresponding to a resistance of thememory cell to the second or third reference voltage.
 53. The method ofclaim 51, wherein the determining step comprises the steps of: if thereadout voltage corresponding to a resistance of the memory cell isgreater than the first reference voltage: determining that a first bitof the multi-bit value is 1; and if the readout voltage corresponding toa resistance of the memory cell is greater than the third referencevoltage, determining that a second bit of the multi-bit value is 1 and,otherwise, determining that the second bit of the multi-bit value is 0,and if the readout voltage corresponding to a resistance of the memorycell is not greater than the first reference voltage: determining that afirst bit of the multi-bit value is 0; and if the readout voltagecorresponding to a resistance of the memory cell is greater than thesecond reference voltage, determining that a second bit of the multi-bitvalue is 1 and, otherwise, determining that the second bit of themulti-bit value is
 0. 54. The method of claim 51, wherein a readoutvoltage corresponding to a resistance of the memory cell greater than 0but less than the second reference voltage corresponds to a multi-bitvalue of 00, a readout voltage greater than the second reference voltagebut less than the first reference voltage corresponds to a multi-bitvalue of 01, a readout voltage greater than the first reference voltagebut less the third reference voltage corresponds to a multi-bit value of10, and a readout voltage greater than the third reference voltagecorresponds to a multi-bit value of
 11. 55. A sense amplifier forreading a multi-bit value stored in a resistive memory cell havingmultiple level resistance states, the sense amplifier comprising: aplurality of current sensing comparators configured to compare a readoutcurrent corresponding to a resistance of the memory cell to a pluralityof reference currents corresponding to reference resistances.
 56. Thesense amplifier of claim 55, wherein the plurality of current sensingcomparators comprise: a first current sensing comparator configured tocompare the readout current corresponding to a resistance of the memorycell to a first reference current approximately equal to ½ of a readoutcurrent corresponding to a reference resistance; a second currentsensing comparator configured to compare the readout currentcorresponding to a resistance of the memory cell to a second referencecurrent approximately equal to ⅙ of a readout current corresponding to areference resistance; and a third current sensing comparator configuredto compare the readout current corresponding to a resistance of thememory cell to a third reference current approximately equal to ⅚ of areadout current corresponding to a reference resistance.
 57. The senseamplifier of claim 56, wherein an output of the first current sensingcomparator corresponds to a first bit of the multi-bit value.
 58. Thesense amplifier of claim 56, wherein outputs of the second and thirdsensing comparators correspond to a second bit of the multi-bit value.59. The sense amplifier of claim 56, further comprising: an invertercoupled to the first current sensing comparator; a first AND gatecoupled to the inverter and the second current sensing comparator; asecond AND gate coupled to the first and third current sensingcomparators; and an OR gate coupled to the first and second AND gates.60. The sense amplifier of claim 59, wherein an output of the OR gatecorresponds to a second bit of the multi-bit value.